IBM Develops New 3-D Chip Stacking Technology

IBM Wafer Showing 3-D Chip Stacking Technology

IBM says it has found a new way to make computer chips that greatly reduces the size of the overall chip package and speeds up the rate of data flow. It’s a three-dimensional technique that could extend Moore’s Law beyond its expected limits.

This 3-D chip stacking is called “through-silicon vias.” It allows various chip components to be packed much closer together for faster, smaller, and lower-power systems.

With this IBM breakthrough it is now possible to move from horizontal 2-D chip layouts to 3-D chip stacking, which takes chips and memory devices that traditionally sit side by side on a silicon wafer and stacks them together on top of one another.

The “vias,” which are essentially vertical connections etched through the silicon wafer and filled with metal, eliminates the need for long metal wires to connect the chips together.


Published by Chris Malinao

Chris teaches Lightroom as workflow software to photography students at the FPPF, Federation of Philippine Photographers Foundation. He also teaches smartphone photography.